Integrated circuits and other electronic devices can include input and/or output (I/O) connections for transmitting and receiving signals. As signal transmission speeds have increased, impedance matching has become an increasingly important feature in such devices. Matching impedance with external package and/or circuit board traces can improve the signal integrity and performance of both a signal transmitter and receiver.
In order to match signal line impedance, I/O circuits can include variable impedance circuits that can be adjusted as needed to match a sensed reference impedance value. Such circuits typically include a pull-up array of impedance devices (e.g., resistors) and/or a pull-down array of impedance devices (e.g., resistors). By selectively enabling such impedance devices, the impedance presented at the I/O can be calibrated to provide a target impedance.
One circuit that can be used in calibrating I/Os is a variable impedance sense (VIS) circuit. A VIS circuit can be used in I/O circuits to match the impedance of pull-up and pull-down arrays to an impedance of an external trace by sensing the resistance of an external reference impedance (e.g., reference resistor). The accuracy of impedance sense and matching circuit can be limited by the architecture and various error sources.
To better understand various features of the disclosed embodiments, a conventional VIS circuit will now be described with reference to FIG. 13.
A VIS circuit 1300 can include an external calibrating resistor RQ that is utilized to calibrate pull-up (PU) arrays 1302-0 and 1302-1, as well as a pull-down (PD) array 1304. PU arrays (1302-0 and 1302-1) and PD array 1304 are understood to be replicas of PU and PD arrays of actual I/O circuits (not shown) for which impedance matching is employed.
Each PU array and PD array can be composed of several pull-up and pull-down legs arranged in parallel. Each leg can represent a unit resistance, which can be established by a combination of transistors and/or a resistor. An impedance of a PU array or PD array can be set by turning on the appropriate number of legs in parallel. FIG. 13 shows a digital value (pu_dac[k:0] and pd_dac[k:0]) for both PU and PD arrays.
The VIS circuit 1300 also shows a switch circuit 1306. A switch circuit 1306 can selectively connect a reference voltage Vref, and voltages generated by PU array 1302-0, or PD array 1304 to inputs of a high gain comparator 1308. The switch circuit 1306 shown includes four switch elements SW_PU1, SW_PU2, SW_PD1, and SW_PD2.
Comparator 1308 has an output connected to a comparator register 1310. A comparator register 1310 can store an output value generated by comparator 1308.
The VIS circuit 1300 of FIG. 13 includes a calibration loop 1312 for a PU array as well as a calibration loop 1314 for a PD array. Further, the VIS circuit 1300 generates impedance matching values utilizing a successive approximation register (SAR) technique, and so includes SAR/counters (SAR/Counter) 1316-0 and 1316-1 for both such loops (1312 and 1314). A resulting value generated in the SAR/Counters 1316-0 and 1316-1 can be stored in update registers 1318-0 and 1318-1, respectively.
As is well understood, in a successive approximation technique, a “most” significant impedance leg can be switched into the circuit to create a voltage divider in conjunction with a reference impedance (e.g., RQ). A resulting voltage generated can be compared against a reference voltage. If the voltage is greater than the reference voltage (as determined by a comparator) a most significant bit can be set to a particular value (e.g., 1 or 0). In following cycle, a next significant impedance leg can be switched into the circuit to determine the value of the next most significant bit. This can continue until a final code is generated.
In the arrangement of FIG. 13, SAR/Counters (1316-0 and 1316-1) can operate as successive approximation registers or as up/down counters based on the mode of operation and the comparator output. The particular mode of operation can be established by control block 1320.
In an initial calibration cycle, a control block 1320 operates SAR/Counters (1316-0 and 1316-1) as successive approximation registers. However, in an update cycle (described in more detail below), SAR/Counters (1316-0 and 1316-1) can operate as up/down counters.
Final codes generated by VIS circuit 1300 (pucode[k:1] and pdcode[k:1]) can be provided to other I/O circuits via final update registers 1322-0 and 1322-1. As can be seen, and as will be discussed in more detail below, final codes (pucode[k:1] and pdcode [k:1]) can be generated by dropping a least significant bit (pu_dac[0] and pd_dac[0]) of a code stored in update registers 1318-0 and 1318-1, respectively.
The operation of the conventional VIS circuit 1300 will now be described.
A VIS circuit 1300 can be conceptualized as including two closed loops; one for the PU array calibration 1312 and another for the PD array calibration 1314. Each loop can include a resistive voltage divider digital-to-analog converter (DAC) and analog-to-digital converter (ADC). In the case of PU loop 1312, the DAC is formed by PU array 1302-0, which receives a digital code (pu_dac[k:0]), and reference resistor RQ, and provides a resulting analog voltage on reference node 1324. In the case of PD loop 1314, the DAC is formed by PU array 1302-1 and PD array 1304, which receives a digital code (pd_dac[k:0]), and provides a resulting analog voltage on reference node 1326.
In the case of PU loop 1312, the ADC is an SAR type ADC formed by comparator 1308, comparator register 1310, and SAR/Counter 1316-0, as controlled by control block 1320. Similarly, in the case of PD loop 1314, the ADC is an SAR type ADC formed by comparator 1308, comparator register 1310, and SAR/Counter 1316-1, as controlled by control block 1320.
In a calibration of the PU loop 1312, VIS circuit 1300 can determine a binary output code (pu_dac[k:0]) for PU arrays in the device by calibrating PU array 1302-0 against external reference resistor RQ. In a calibration of PD loop 1314, VIS circuit 1300 can determine a binary output code (pd_dac[k:0) for PD arrays in the device by calibrating PD array 1304 against an already calibrated PU array 1302-1. That is, once a calibrated pull-up code (pu_dac[k:0]) has been generated, such a code can be applied to PU array 1302-1, to enable it to act as a reference resistor for PD array 1304.
Initially, a PU loop 1312 can be enabled and a PD loop 1314 can be disabled. In such a state, switch elements SW_PU1/2 can be closed (i.e., low impedance) and switch elements SW_PD1/2 can be open (i.e., high impedance). An output of the PU voltage divider (1302-0/RQ) on reference node 1324 can be connected to a positive terminal of comparator 1308 and a reference voltage (Vref) can be connected to a negative terminal of comparator 1308. Resulting outputs of the comparator C1 can be used by SAR/Counter 1316-0 in an SAR type binary search algorithm to determine binary output code for the PU array (pu_dac[k:0]). In such an operation, comparator 1308 and SAR/Counter 1316-0 can act as an SAR ADC, which quantizes the analog input (output of the PU voltage divider) one bit (e.g., reference resistor leg) at a time. For each bit (starting from the MSB of pu_dac[k:0]), the ADC turns on the bit and checks the output of the DAC (PU voltage divider). If the output of comparator 1308 is HIGH, the bit can be turned off and the next bit can be turned on. If the output of comparator 1308 is LOW, a bit can be left on and the next bit can be turned on. This process can be repeated until all (in this case k+1) bits of the pull-up binary code (pu_dac[k:0]) have been determined. A final pull-up binary code can represent the number of pull-up legs required to match the impedance of PU array 1302-0 to the external resistor RQ.
Once PU array 1302-0 has been calibrated, the resulting code stored in update register 1318-0 can be output to reference PU array 1302-1, and PU loop 1312 can be disabled. Subsequently, PD loop 1314 can be enabled and, the same procedure (SAR technique) can be used to calibrate PD array 1304. Accordingly, switches SW_PD1/2 can be closed and switches SW_PU1/2 can be open. An output of the PD voltage divider (1302-1/1304) at reference node 1326 can be connected to a negative terminal of comparator 1308 and reference voltage Vref can be connected to a positive terminal of comparator 1308. A final pull-down binary code (pd_dac[k:0]) can be stored in update register 1318-1, and can represent the total number of pull-down legs required to match the impedance of PD array 1304 to calibrated PU array 1302-1. This can complete an initial calibration cycle.
However, while one set of calibration codes can provide an initial impedance match for I/Os of a device, operating conditions can result in changes (i.e., drift) in circuit components. In order to account for the variations in temperature and voltage, the pull-up and pull-down binary output codes (pu_dac [k:0] and pd_dac [k:0]) can be updated every “P” number of clock cycles. Such updates can be 1 bit updates that introduce a maximum of 1 LSB in either an up direction (increment) or down direction (decrement). Such an operation can be an update cycle or update mode operation.
Referring still to FIG. 13, during an update mode operation, an SAR/Counter (1316-0 and/or 1316-1) can operate as an up-down counter according to an output of comparator 1308. A PU array 1302-0 can be updated first, with a resulting code being applied to PU array 1302-1. A PD array 1304 can then be updated. In more detail, during an update operation of a PU array 1302-0, if an output of comparator 1308 is ‘1’, indicating that there has been some decrease in the impedance of the PU array 1302-0, pull-up binary code (pu_dac[k:0]) can be decremented by 1. Conversely, if an output of comparator 1308 is ‘0’, indicating an increase in the impedance of PU array 1302-0, pull-up binary code (pu_dac[k:0]) can be incremented by 1. Once a pull-up binary code is updated, a pull-down binary code (pd_dac[k:0]) can be updated in the same general way. Such codes values can then be forwarded to actual I/Os of the device.
As noted briefly above, the arrangement of FIG. 13 shows an example in which a binary output code of k+1 bits is generated, but only k such bits are used as values to provide impedance matching at actual I/Os. That is, an LSB bit of binary output codes (pu_dac [k:0] and pd_dac [k:0]) can be dropped and the remaining k bits (pu_dac[k:1] and pd_dac[k:1] are stored in final update registers (1322-0 and 1322-1) and then provided to I/O driver circuits.
The dropping of an LSB can occur in order to reduce noise in a VIS circuit 1300. In the case of frequent update cycles and especially for continuous updates (updates at every clock cycle), an LSB bit within each output code can toggle every update cycle (even if there is no significant temperature or voltage variation). Such a bit can be called a “chatter” bit. A chattering of an LSB bit can cause significant noise in a driver circuit and adversely affect its performance.
Accordingly, in cases where the noise due to the chattering bit dominates the accuracy gained by the 1 LSB, the LSB bit can be dropped and the remaining bits can be utilized to match impedance of actual I/O driver circuits. This can be the same as the I/O driver circuits getting all the bits, but with the last bit (LSB) being always ‘0’ (turned OFF). In FIG. 13, an LSB bit can be dropped only on a final code that is sent to I/O driver circuits and not on the code inside the VIS circuit. Thus, dropping of an LSB bit can have no effect on the general operation of the operation of calibration loops 1312 and 1314.
Referring now to FIG. 14, a conceptual operation of the VIS circuit of FIG. 13 is shown in a flow diagram. FIG. 14 shows an initial calibration cycle, as well as update operations described above. Within the flow diagram 1400, “STEP B1” refers to implementation of a binary search SAR technique during an initial calibration cycle. STEP B2 refers to the operation of dropping an LSB bit from resulting binary codes. STEP B3 represents an up/down counter operation during an update operation. STEP B4 represents the operation of dropping the LSB bit during an update operation
While the conventional arrangement shown in FIGS. 13 and 14 can provide adequate results under some operating conditions, such an arrangement can have drawbacks.
First, an input offset voltage can be a significant source of error in the VIS circuit 1300. An input offset voltage can arise from numerous sources, including but not limited to an input offset at the inputs of comparator 1308, an error in reference voltage Vref, and/or an overdrive voltage of the comparator 1308. Thus, as the accuracy requirements for impedance matching become more precise, the error induced due to such an input offset can result in an unacceptably inaccurate response. Still further, the effect of a comparator input offset on overall matching accuracy can increase as the operating supply voltage decreases. As a result, at such lower power supply levels, an offset voltage can become comparable to the resolution of SAR ADC (i.e., be equivalent to 1 LSB).
Second, in the conventional arrangement shown, the VIS circuit 1300 does not differentiate between a positive and negative input offset. However, in such an arrangement a worst-case error is not the same when an input offset is a positive voltage as compared to when an input offset is a negative voltage. In particular, a largest worst-case error can occur when an input offset is a negative voltage. The following discussion illustrates the effect of such input offsets on the accuracy of a conventional VIS circuit 1300.
Referring still to FIG. 14, STEP B1, B2 and B4 will always move the impedance of the array in the downward direction with reference to an external resistor RQ. As a result, following quantization and dropping of an LSB, a conventional VIS circuit 1300 can turn on a smaller (larger) number of legs than an ideal case, thereby setting a resistance of a PU array to a higher (lower) value than a target resistance (RQ).
In the case of a positive input offset, because the direction of the offset is upward, an error contributed due to the input offset is compensated for by the steps moving in the opposite direction. Thus, a worst-case error resulting from a positive comparator input offset can be calculated to be (2LSB−offset), where “offset” in this equation refers to a total error due to the input offset voltage.
In the case of negative input offset, since the direction of the offset is downward, it adds to the error contributed by the above described steps. As a result, a worst-case error can be calculated to be (2LSB+offset).
Details of the above error calculation are shown in FIG. 15. FIG. 15 is a graphical illustration showing propagation of the worst-case error due to the input offset voltage during STEP B1 through STEP B4 shown in FIG. 14. Solid horizontal lines labeled as “RQ” represent a target impedance (e.g., system trace impedance) to be matched. Top waveforms 1500 shows a worst-case error when an input offset is positive, and bottom waveforms 1502 show a worst-case error when an input offset is negative.
Referring still to FIG. 15, STEP B1 represents a VIS circuit implementing the SAR technique to successively turn on legs (e.g., bits) in a PU array until the comparator trips. When the comparator trips, the SAR can reset back to the previous step. Accordingly, a maximum error that can occur with such an operation can be 1 LSB. Such an error can occur when a target value RQ is actually close to the bit that causes the comparator to trip.
STEP B2 represents the operation of dropping an LSB. Such a step can introduce a maximum error of 1 LSB. Thus, a resistance at the end of STEP B2 can represent an actual selected resistance for I/O driver arrays during an initial calibration cycle.
As can be seen from the waveform sets of FIG. 15, in the case of a positive input offset, STEP B1 and STEP B2 can both move in direction opposite to the direction of the offset. As a result, the effect of the error due to the input offset can be “(2LSB−offset)” during an initial calibration cycle.
In contrast, in the case of a negative input offset, both STEP B1 and STEP B2 can move in the same direction as the input offset, thereby adding to the resulting error. As a result, a worst-case error with a negative input offset can be “(2LSB+offset)” during the initial calibration cycle.
As noted above, once an initial calibration cycle is complete, output codes can be adjusted periodically to account for any variations in temperature or voltage. A maximum allowed variation can be set to 1 LSB. Thus, such variations can cause an impedance established by the above steps to drift up (a decrease in the resistance of the PU/PD array) or drift down (increase in the resistance of the PU/PD array) by a maximum of 1 LSB.
Referring still to FIG. 15, during STEP B3, a comparator can re-evaluate an output code to determine a direction of a drift, and move a code count 1 LSB in a direction that compensates for such drift. FIG. 15 shows error propagation for both possible update cases (Drift-Up and Drift-Down). A maximum error that can occur during STEP B3 can be +1 LSB, in the case of downward drift, and −1 LSB, in the case of an upward drift, because a counter can be set to change a code value by only 1 LSB bit, either up or down.
STEP B4 represents the dropping of an LSB during an update operation. A maximum error during this operation can be 1 LSB. As can be seen in FIG. 15, a worst-case error during an update operation can be (2LSB−offset) in the case of a positive offset (1500) and (2LSB+offset) in the case of a negative offset.
To summarize, a worst-case error in the conventional VIS circuit 1300 can be 2LSB−offset, in the case of a positive input offset, and 2LSB+offset, in the case of a negative input offset. These results are further summarized in the table shown in FIG. 16.
In light of the above, it would be desirable to arrive at a circuit and/or method of variable input sensing that can take into account any input offset inherent in the sensing circuits. Further, it would also be desirable to arrive at a VIS circuit and/or method that can compensate for differences in error arising from the type of inherent offset (e.g., positive or negative) inherent in the sensing circuit.